1. Field of the Invention
The present invention relates generally to data communications, and more particularly but not exclusively to methods and apparatus for recovering an embedded clock and detecting data from a data stream.
2. Description of the Background Art
A typical data communications system comprises a transmitter, a communication media, and a receiver. Data may be modulated at the transmitter, transmitted over the communication media, and then demodulated at the receiver. Non-return to zero (NRZ) is an example modulation scheme used in digital data communications. In FIG. 1, an example waveform of an NRZ modulated signal is shown above its corresponding binary data representation. In an NRZ waveform, a logical 1 has a high voltage with a pulse width of T, and a logical 0 has a low voltage also with a pulse width of T. The pulse width T is the reciprocal of the data rate. An NRZ modulated signal has both clock and data information, and is thus not transmitted with a separate clock signal.
FIG. 2 schematically shows an example communications system employing NRZ modulation. The communications system of FIG. 2 includes a transmitter 210, a communication media 220, and a receiver 230. The transmitter 210 includes an encoder 212, such as an 8B10B encoder, for encoding input binary data to another binary data sequence. A digital to analog converter (DAC) 213 in the transmitter 210 converts the logical (i.e., digital) output of the encoder 212 to analog form. The analog voltage signal from DAC 213 is transmitted over the communication media 220 (e.g., transmission line) to the receiver 230 as a data stream. In the example of FIG. 2, the receiver 230 includes a receiver front-end module 232, a clock data recovery (CDR) module 236, and a decoder 238. The front-end module 232 amplifies the voltage signal received over the communication media 220 (i.e., the input signal to the receiver 230), and generates an output voltage signal V. The voltage signal V is input to the CDR module 236, which recovers the NRZ encoded data D and the clock CLK used by the transmitter 210 and embedded in the NRZ waveform. The decoder 238 generates an output binary data sequence by decoding the recovered data D.
FIG. 3 shows a schematic diagram of a conventional CDR module 300. The CDR module 300 is an example implementation of the CDR module 236 shown in FIG. 2. The CDR module 300 is a phase lock loop (PLL) that comprises a binary phase detector (BPD) 310, a loop filter (LF) 320, and a voltage-controlled oscillator (VCO) 330. The output of the VCO 330 is a recovered clock CLK that tracks the clock embedded in the voltage signal V, which is the input to the CDR module 300. The BPD 310 compares the phase difference between the reference clock embedded in the voltage signal V and the recovered clock CLK, and generates a phase error signal E. A subsequent loop filter (LF) 320 filters the phase error signal E and generates a control signal C. The control signal C controls the frequency, and therefore also the phase, of the VCO 330. For example, if the recovered clock CLK is too fast compared to the reference clock embedded in the voltage signal V, the BFD 310 will generate a negative pulse in the phase error signal E and cause the frequency of the VCO 330 to decrease; if the recovered clock CLK is too slow compared to the reference clock embedded in the voltage signal V, the BFD 310 will generate a positive pulse in the phase error signal E and cause the frequency of the VCO 330 to increase. The frequency of the VCO 330 is thus adjusted in a closed-loop manner so that the frequency (and therefore also the phase) of the recovered clock CLK will track the frequency (and therefore also the phase) of the reference clock embedded in the voltage signal V.
As in the case of any clocking signal, the recovered clock CLK has two edges: a rising edge and a falling edge. In one embodiment, the rising edge is used and referred to as the leading edge, while the falling edge is used and referred to as the trailing edge. In other embodiments, the falling edge is used and referred to as the leading edge, while the rising edge is used and referred to as the trailing edge. Choosing which edge of the clock to use as the leading or trailing edge is a matter of design choice.
The primary function of a PLL, such as the CDR module 300, is to adjust the frequency (and therefore also the phase) of a recovered clock CLK so that the leading edge of the recovered clock CLK is aligned with the middle of the NRZ data represented by the voltage signal V, while the trailing edge of the recovered clock CLK is aligned with the data transition. In the CDR module 300, the BPD 310 determines the relative timing relationship between the data transition and the trailing edge of the recovered clock CLK.
The BPD 310 comprises four data flip flops (DFF) 312a, 312b, 312c, and 312d, and a BPD logic 314. The DFF 312a samples the NRZ data represented by the voltage signal V using the leading edge of the recovered clock CLK, and generates the data D. The DFF 312c samples the transition of the NRZ data represented by the voltage signal V using the trailing edge of the recovered clock CLK, and generates the transition sample S. The data D is further sampled by the DFF 312b using the leading edge of the recovered clock CLK, resulting in data P, which is the data D of the previous clock cycle. The transition sample S is further sampled by the DFF 312d using the leading edge of the recovered clock CLK, resulting in sample Q, which is the same as sample S but synchronized with the leading edge of the recovered clock CLK. If there is no data transition, i.e. there are two consecutive 1's or 0's in the NRZ data, the transition sample S will be identical with both the data D and the data P and no timing information is revealed. If there is a data transition, i.e. (D==0 and P==1) or (D==1 and P==0), timing relationships can be determined by comparing the synchronized transition sample Q with the data D. If the transition sample is sided with the data before transition, i.e. Q==P, it indicates the transition is sampled too early. On the other hand, if the transition sample is sided with the data after transition, i.e. Q==D, it indicates the transition is sampled too late. The BPD logic 314, which receives the data D, the sample P, and the sample Q, performs the aforementioned analysis to generate the phase error signal E based on: (1) detecting whether there is a data transition by comparing the data D with its previous sample P, and (2) detecting which end of the transition the transition sample is sided with by comparing the sample Q with the data D or comparing the sample Q with the sample P when there is a data transition.
The phase error signal E generated by the BPD logic 314 is a ternary signal (i.e. it has three possible values: +1, 0, −1). There are three possibilities: (1) E=0, indicating timing error is unknown due to no data transition (this occurs when D==P); (2) E=+1, indicating the recovered clock is too late compared to the reference clock embedded in the NRZ data (this occurs when D≠P and D==Q); and (3) E=−1, indicating the recovered clock is too early compared to the reference clock embedded in the NRZ data (this occurs when D≠P and D≠Q). The phase error signal E is thus indicative of a phase relationship between the reference clock signal embedded in the NRZ data and the recovered clock CLK generated by CDR module 300.
Although workable, the CDR module 300 is susceptible to performance degradation due to limited circuit speeds, in particular when the NRZ data rate is very high. In other words, because electrical circuits do not have infinite speed, most circuits will have difficulty processing very high speed data streams. Ideally, the phase error signal E of the BPD logic 314 is a ternary signal consisting of many pulses, either positive or negative, that have the same magnitude but varying widths. FIG. 4 shows an ideal waveform of a phase error signal E (labeled as “Ideal E”) compared to its practical (i.e. actual; labeled as “practical E”) waveform as generated by the BPD logic 314. In FIG. 4, the ideal phase error signal E contains a positive pulse 410 of width T, a negative pulse 412 of width 2T, a negative pulse 414 of width T, a positive pulse 416 of width 3T, and a negative pulse 418 of width T. Ideally, the total area of each pulse should be proportional to its pulse width. Due to finite circuit speeds, each pulse in the practical phase error signal E, positive or negative, is distorted. In particular, the total area of each pulse in the practical phase error signal is still related, but no longer proportional, to its pulse width. For example, a practical pulse with a pulse width of T (e.g., pulses 420, 424, 428) has an area that is relatively small. A practical pulse with a pulse width of 2T (e.g., pulse 422) has an area that is more than two times larger than that of a practical pulse with a pulse width of T; a practical pulse with a pulse width of 3T (e.g., 426) has an area that is more than three times larger than that of a practical pulse with a pulse width of T, and so on. Therefore, as the pulse width of the phase error signal gets wider, the distortion due to finite circuit speeds becomes more significant. The distortion in phase error signal results in excessive clock jitters at VCO 330 output and degrades the system performance.
What is needed is a method to correct the distortion in phase error signal due to finite circuit speeds.